Offer evaluation from Cadence Design Systems
Hi All, I have 6 years of experience in digital design verification at Intel (arizona) with current tc $166k ($125k base, $12k bonus, $29k rsu). Here’s my new offer from Cadence design systems (san jose) as application engineer for eda tool. Tc $189k Base $148k Bonus+rsu $41k matching with existing comp at intel. Since it is in Sanjose, should i be asking for more? I would appreciate if : 1. people can suggest appropriate comp based on this profile so i can negotiate better. 2. Suggest if application engg profile is good to switch from design verification. 3. Any negative inpact if i want to switch back to design verification in future?
this is a net reduction due to higher col
Profile downgrade plus TC downgrade (if you account COL)
Application engineer is a downgrade for you. Unless you are facing CPM stay.
Not in CPM but I don’t like the team anymore. So i was thinking of getting this position for now and return to intel after a year once everything becomes normal. Will returning back impact my dv profile?
It is relatively difficult to get out of service company and get in product.
Imba lowball
I would not recommend going application engineer in Cadence, that would be huge career downgrade and no good perspectives for future. Basically you will be support. Will make it tougher for you to switch back.
Year back I had base of 165k from different company, FYI. This is lowball and AE is career backstep. Unless you are in dire situation, stay and interview more.
Come to bay area only if you have atleast 30% jump in salary to live a similar lifestyle. You will need a 2nd salary to own a decent home.
With 6 YOE, it should be close to 250k. This is lowball. Just for your reference..I am digital design engineer in bay area with 7-8 YOE..TC 310k
Is it fair to understand that design engineers have higher comp than verification eng? Or that is a misunderstanding?
DV make more then DIgital design